1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a transflective LCD device that selectively uses reflective and transmissive modes.
2. Discussion of the Related Art
Generally, transflective LCD devices have functions of transmissive and reflective LCD devices at the same time. Since the transflective LCD devices can use both light of a backlight, and natural or artificial light of the exterior, the transflective LCD devices are not restricted from circumstances and a power consumption of the transflective LCD devices is reduced.
FIG. 1 is a schematic perspective view of a conventional transflective color LCD device.
In FIG. 1, the conventional transflective LCD device 11 includes an upper substrate having a transparent common electrode 13 on a black matrix 16 and a color filter layer 17, and a lower substrate 21 having a switching device “T” and gate line 25 and data line 39. The lower substrate 21 also has a pixel region “P” where a reflective plate 49 (of FIG. 2) that has a transmissive hole “A” and a transparent electrode 61 (of FIG. 2) are formed. The pixel region “P” is divided into a transmissive portion “B” and a reflective portion “D”. Further, a liquid crystal layer 14 is interposed between the upper and lower substrates 15 and 21.
FIG. 2 is a schematic cross-sectional illustration of a conventional transflective LCD device.
In FIG. 2, a conventional transflective LCD device 11 includes an upper substrate 15 where a common electrode 13 is formed, a lower substrate 21 where a reflective plate 49 having a transmissive hole “A” and a transparent electrode 61 are formed, a liquid crystal layer 14 interposed between the upper and lower substrates 15 and 21, and a backlight 41 under the lower substrate 21. When the conventional transflective LCD device 11 is operated in a reflective mode, external natural or artificial light is used as a light source.
Operation of the conventional LCD device for reflective and transflective modes will be illustrated considering the above-mentioned structure.
In the reflective mode, the conventional transflective LCD device uses external natural or artificial light. Light “F2” incident on the upper substrate 15 is reflected at the reflective plate 49 and passes through the liquid crystal layer 14. The liquid crystal molecules in the liquid crystal layer 14 are aligned by an electric field between the reflective plate 49 and the common electrode 13. Here, the transmission of the light “F2” through the liquid crystal layer 14 is controlled according to the alignment of the liquid crystal layer 14 and images are displayed.
In the transmissive mode, light “F1” from the backlight 41 under the lower substrate 21 is used as a light source. The light “F1” emitted from the backlight 41 is incident on the liquid crystal layer 14 through a transparent electrode 61. Transmission of the light “F1” through the liquid crystal Layer 14 is controlled according to an alignment of the liquid crystal molecules in the liquid crystal layer 14 driven by an electric field between the transparent electrode 61 under the transmissive hole “A” and the common electrode 13. Thus, images can be displayed.
FIG. 3 is a schematic plan view of an array substrate for a conventional transflective LCD device.
In FIG. 3, a lower substrate 21, referred to as an array substrate, includes a thin film transistors (TFT) “T” in matrix. The TFTs act as switching devices. Each TFT “T” is connected to a gate line 25 and a data line 39. A gate pad 27 is formed at one end of the gate line 25, and the gate pad 27 is wider than the gate line 25. A data pad 41 that is wider than the data line 39 is formed at one end of the data line 39. The gate pad 27 and the data pad 41 contact a transparent gate pad terminal 63 and a transparent data pad terminal 65, respectively. External signals are directly applied to the transparent gate pad terminal 63 and the transparent data pad terminal 65. An insulating layer is interposed between the gate line 25 and the data line 39. An align key 80 is formed at a non-display region of the lower substrate 21 during a process of forming the gate line 25. The align key 80 provides a basis for aligning all patterns over the gate line 25 at a correct position. Here, a pixel region “P” is defined by the gate line 25 and the data line 39. A storage capacitor “C” is formed over a portion of the gate line 25 and connected in parallel to a transparent pixel electrode of the pixel region “P”. The TFT “T” includes a gate electrode 23, an active layer 31, and source and drain electrodes 35 and 37. Here, a transparent electrode 61 and a reflective plate 49 having a transmissive hole constitute a transflective pixel electrode of the pixel region “P”.
FIGS. 4A to 4C are schematic cross-sectional views illustrating a fabricating process of an array substrate for a conventional transflective LCD device. FIGS. 4A to 4C are taken along the line IV—IV of FIG. 3.
In FIG. 4A, after a gate electrode 23, a gate line 25 and a gate pad 27 are formed on a substrate 21, a gate insulating layer 29, i.e., a first insulating layer, is formed thereon. The gate pad 27 is disposed at one end of the gate line 25. The gate insulating layer 29 of about 4000 Å in thickness including one of inorganic material group including silicon nitride (SiNx) and silicon oxide (SiO2). Next, an active layer 31 and an ohmic contact layer 33 of an island shape are formed on the gate insulating layer 29 over the gate electrode 23. Next, source and drain electrodes 35 and 37 are formed on the ohmic contact layer 33. A data line 39 connected to the source electrode 35; a data pad 41 at one end of the data line 39; and a capacitor electrode 43 of an island shape over the gate line 25 are formed at the same time.
In FIG. 4B, a planarization layer 45, when is a second insulating layer, is formed on an entire surface of the substrate 21 through depositing one of a transparent organic insulating material group including benzocyclobutene (BCB) and acrylic resin. A third insulating layer 47 of one of an inorganic insulating material group including SiNx and SiO2 is sequentially formed on the planarization layer 45 through a plasma enhanced chemical vapor deposition (PECVD) method. The third insulating layer 47 of the inorganic material is further formed on the planarization layer 45 of the organic material to prevent fine organic materials from detaching from the surface of the organic material during the process of forming a reflective plate 49. Defects may occur at a surface of the planarization layer 45 due to high speed metal ions during the process of forming the reflective plate 49 on the planarization layer 45 by using a sputtering method. Fine organic materials detaching from those defects may contaminate a chamber. A reflective plate 49 having a transmissive hole “A” at the pixel region “P” is formed on an the third insulating layer 47 through depositing by a PECVD method and patterning aluminum (Al) or Al alloy.
In FIG. 4C, a passivation layer 51, which is a fourth insulation layer, having a drain contact hole 53, a storage contact hole 55, a gate pad contact hole 57 and a data pad contact hole 59 is formed on an entire surface of the substrate 21 through depositing and patterning one of inorganic insulating material group including SiNx and SiO2. The drain contact hole 53 exposes the drain electrode 37; a storage contact hole 55 exposes the capacitor electrode 43; a gate pad contact hole 57 exposes the gate pad 27; and a data pad contact hole 59 exposes the data pad 41. Next, a pixel electrode 61 connected to the drain electrode 37 and to the capacitor electrode 43 is formed at the pixel region “P” through depositing and patterning one of a transparent conductive metallic material group including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). A gate pad terminal 63 contacting the gate pad 27 and a data pad terminal 65 contacting the data pad 41 are formed at the same time. An align key 80 (of FIG. 3) is simultaneously formed at a non-display region during a process of forming the gate line 25 and used to align a mask and the substrate 21.
FIG. 5 is a schematic cross-sectional view showing a structure of an align key. FIG. 5 is taken along the line V—V of FIG. 3.
In FIG. 5, an align key 80 of the same material as the gate line 25 and the gate electrode 23 is simultaneously formed on a substrate 21 during a process of forming the gate line 25 and the gate electrode 23. Generally, the align key 80 is disposed at a non-display region where images are not displayed. First, second, third and fourth insulating layers 29, 45, 47 and 51 are sequentially formed on the align key 80.
FIGS. 6A to 6D are schematic cross-sectional views showing a process of forming a reflective plate by using an align key. FIGS. 6A to 6C are taken along the line V—V.
In FIG. 6A, a metal layer 48 is formed on a third insulating layer 47 through depositing one of Aluminum and Aluminum alloy. After forming a photoresist (PR) layer 82 on the metal layer 48, an exposing process is performed with a first mask 84 disposed over the PR layer 82. The first mask 84 has a transmissive portion “G” corresponding to the align key 80.
In FIG. 6B, after a developing process is performed, a portion “H” of the metal layer 48 is etched to form a reflective plate 49 (of FIG. 6D) without misalignment. A second mask 86 (of FIG. 6C) for patterning the reflective plate 49 (of FIG. 6D) is aligned with the align key 80 of the lowest layer on the substrate 21. That is, the second mask 86 (of FIG. 6C) is precisely disposed through aligning another align key 87 (of FIG. 6C) of the second mask 86 (of FIG. 6C) with the align key 80 of the substrate 21 by using an aligner (not shown). The aligner perceives an aligned state by irradiating light to another align key 87 (of FIG. 6C) of the second mask 86 (of FIG. 6C) and the align key 80 of the substrate 21 and receiving the reflected light. If the aligner does not detect the align key 80 of the substrate 21, bad patterns are formed due to a misalignment. Accordingly, the align key 80 of the substrate 21 may be formed to have an uneven shape. If a surface of layers over the align key 80 is flat, the layers may be transparent so that light can pass through the layers. If layers over the align key 80 are opaque, the layers may have an uneven surface according to a step of the align key 80 so that align key 80 can be indirectly exposed. In the process of forming the reflective plate, however, since the opaque metal layer 48 is formed over a second insulating layer 45 planarizing a surface, the align key 80 cannot be detected. Therefore, as shown in FIG. 6B, a portion of the metal layer 48 corresponding to the align key 80 should be etched first. After the portion of the metal layer 48 is eliminated, since the first, second and third insulating layers 29, 45 and 47 are transparent, the light irradiated from the aligner (not shown) passes through the first, second and third insulating layers 29, 45 and 47 so that the align key 80 can be detected.
In FIG. 6C, a second mask 86 is precisely disposed over the substrate 21 through aligning the align key 87 of the second mask 86 with the align key 80 of the substrate 21. The second mask 86 includes a shielding region “I” corresponding to a reflective plate 49 (of FIG 6D) and a transmissive region “J” corresponding to a transmissive hole “A” (of FIG. 6D).
In FIG. 6D, after a process of exposure and development, the metal layer 48 (of FIG. 6C) is etched to form a reflective plate 49 having a transmissive hole “A.”
In the array substrate for the conventional transflective LCD device, since the organic insulating layer is formed on the TFT, a channel region of the active layer directly contacts the organic insulating layer. A contact property between the organic insulating layer and the active layer is not good. Accordingly, leakage current may be generated and an operating property of the TFT may be degraded due to defects between the organic insulating layer and the active layer.
Further, to prevent a contamination of the chamber by the organic material during the process of depositing the metal layer on the organic insulating layer, an additional inorganic insulating layer may be interposed between the organic insulating layer and the metal layer by a PECVD method. Accordingly, processes become complex and the cost of materials increases.
Moreover, since additional photolithography and etching processes are necessary to expose the align key during the process of forming the reflective plate, the production yield decreases.